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ICs for Information
AN32502A
Power Management IC for Intel PXA250 Application Processor
Overview
This IC is a power management IC developed for Intel PXA250 application processor.
Features
* AN32502A has 2-ch DC-DC converter, 3-ch linear regulator and an interface circuit for power management.
Applications
* PDA, Smart phone
Package
* HQFN 64 pin plastic package (HQFN-64)
Type
* Silicon monolithic Bi-CMOS IC
Publication data: November 2002
SDF00034AEB
1
AN32502A
Ch.5 2.8V 300mA
Set resistor value to limit chrging current not to exceed the limitation of coin battery 330k General purpose output 33p Q8 47k 680k
VB
680k
470k 10k 0.01 FBR1 150k 33k 22k 15k
15k PB2 PB4 PB3 PB1 PB0 PR5 VB1 FBB VREFDET1 FBD1 FBC1 IN1 FB1 1000p SS1 1000p 1000p
Connect to Ch.2 output
REGOUT
LEVEL SHIFT
LT
LEVEL SHIFT
SCP
IN4
PR2
LGND
CT 33p
RT
SS4
VIN
VO1
VO2
10k
22k
nRESET
SGND
0.1
1000p
PR3
1000p
1000p
FB4
Q1: NDS332P ( Fairchild ) Q2: NDS335N ( Fairchild ) Q3: FDC604P ( Fairchild ) Q4: FDC604P ( Fairchild ) Q5: FDC604P ( Fairchild ) Q6: FDC634P ( Fairchild ) Q7: FDC633P ( Fairchild ) Q8: FDC604P ( Fairchild ) L1 : ELL6PM100M ( Matsushuita Electric Compornents ) L2 : ELL6PM100M ( Matsushuita Electric Compornents ) L3 : ELJEA151KF ( Matsushuita Electric Compornents ) D1 to D3: MA2YD23 ( Matsushuita Electric Industrial )
BAT_FLT
Publication data: November 2002
46 44
LEVEL SHIFT CTL logic VB VDD1 LDO DRIVER CTL logic HO1 D1 LO1 Q2 33 OSC PROM BGR VREF PWM VREF 7 BIT DAC Q1 L1 10 POWER ON RESET
48 32 31 30 29
PGND1 VB2
Application circuit example
47
45
43
42
41
40
39
38
37
36
35
34
33
BACKUP
49
VBO
COIN BAT Voltage Det. V REF
COIN BAT
50
COIN BAT CHARGE
Ch.1 1.3V 600mA
VBI
51
from CTL logic
L3 150
47
D3
BACKUP circuit
BO
52
SW REG DRIVER
VREFDET2 V REF from control logic CTL logic VREF LDO to each channel CTL logic
53
BGR
PROM
V REF (for BACKUP)
28 27 26
VB3
Reverse current protection
Note) *: The resistance value is constant setting of E6 series
Q3 LC2 Q4 33 PGND2 330k 680k 47k 33p Ch.2 3.2V 300mA
1000p
PWR_EN (Ch.1 On/Off)
S1
54
I2 C decorder
Ch.2 On/Off
S2
55
VDD1 VB
S3
Ch.3 On/Off
56
Protection circuit SCP SCPO from ch.1 error amp. from ch.4 output detector CTL logic from control logic VREF LDO VREF 1.6V
25 24 23 22
OSC
Control logic
FBR2
S4 Battery voltage detection
SDF00034AEB
from CTL logic to ch.1 ch.4 VREF OSC PWM from control logic CTL logic SW CONTROL VB VDD1
Ch.4 On/Off
57
RGC2 VB4
DATA
58
LC3 Q5 33 1M
59
Ch.3 3.3V 500mA
VDD1 VB
VDD1
60
21 20 19 18
33p PGND3 68k 470k FBR3 VB5 Q6 HC4 L2 10 LC4 0.01 33
TRIG
61
nRESETOUT
62
PS
63
WAKEUP
64
LEVEL SHIFT
17
D2 Q7
33k 33k 33k
4.7k
Ch.4 3.2V 500mA
1 5
2
3
4
6
7
8
9
10
11
12
13
14
15
16
PGND4
0.01
Stabilized DC input
2
AN32502A
Absolute Maximum Ratings
A No. 1 Parameter Storage temperature Operating ambient temperature Operating ambient atmospheric pressure Operating constant gravity Operating shock Supply voltage Symbol Tstg Topr Rating -55 to +125 Unit Note
C C
*1 *1
2
-20 to +75 1.013 x 105 0.61 x 105 9 810
3 4
Popr
Pa
Gopr Sopr
m/s2

5 6
4 900 6.0
m/s2 V
VBAT
7
Supply current
ICC
mA
8
Power dissipation
PD
mW
*1, 2
Operating supply voltage range
VB, VDD1 BACKUP
2.8 V to 5.8 V 2.0 V to 3.2 V
Note) *1: Except for the storage temperature, operating ambient temperature, supply current and power dissipation, all ratings are for Ta = 25C. *2: Refer page 29 *3: Care should be taken when insert this IC (inverted insertion cause destruction.) *4: Care should be taken this IC's surge breakdown voltage.
Publication data: November 2002
SDF00034AEB
3
AN32502A
Electrical Characteristics at VB1 to VB5 = 3.6 V
Note) Ta = 25C2C unless otherwise specified.
B No.
Parameter Ch.1
Symbol
Test circuit
Limits Conditions Min Typ Max
Unit
Note
1
DC-DC converter Output voltage 1
Vch1d1
1
VB = 3.6 V DAC = 1010100B Iout = 200 mA VB = 3.6 V DAC = 1000000B Iout = 200 mA VB = 3.6 V DAC = 1010100B Iout = 200 mA/ 600 mA Output voltage difference VB = 3.4 V/ 5 V Iout = 200 mA Voltage characteristics setting
1.26
1.3
1.34
V
2
DC-DC converter Output voltage 2
Vch1d2
1
1.07
1.1
1.13
V
3
DC-DC converter output voltage
Vch1dd1
1
-30
0
30
mV
4
DC-DC converter Supply voltage characteristics Ch.2
Vch1bb
1
-30
0
30
mV
5
LDO output voltage
Vch2
1
VB = 3.6 V Iout = 100 mA VB = 3.6 V Iout = 100 mA/ 250 mA Output voltage difference VB = 3.4 V/ 5 V Iout = 100 mA Voltage characteristics setting
3.1
3.2
3.3
V
6
LDO output voltage
Vch2d
1
-30
0
30
mV
7
Supply voltage characteristics
Vch2bb
1
-30
0
30
mV
Publication data: November 2002
SDF00034AEB
4
AN32502A
Electrical Characteristics at VB1 to VB5 = 3.6 V (continued)
Note) Ta = 25C2C unless otherwise specified.
B No.
Parameter
Symbol
Test circuit
Limits Conditions Min Typ Max Unit Note
Ch.2 backup circuit 8 9 Backup output voltage Charge voltage Backup battery detection voltage Ch.3 VB = 3.6 V Iout = 100 mA VB = 3.6 V Iout = 100 mA/ 500 mA Output voltage difference VB = 3.4 V/ 5 V Iout = 100 mA Voltage characteristics setting Vch2b1 1 1 COIN BAT = 2.5 V Iout = 2 mA VB = 3.6 V Iout = 10 mA Threshold voltage of detection circuit 3.0 3.2 3.4 V
Vch2c1
2.7
3.0
3.3
V
10
Vch2bkd
1
2.0
2.2
2.4
V
11
LDO output voltage
Vch3
1
3.2
3.3
3.4
V
12
LDO output voltage
Vch3d
1
-30
0
30
mV
13
Supply voltage characteristics
Vch3bb
1
-30
0
30
mV
Ch.4 DC-DC converter output voltage DC-DC converter output voltage VB = 3.6 V Iout = 200 mA VB = 3.6 V Iout = 200 mA/ 500 mA Output voltage difference VB = 3.4 V/ 5 V Iout = 200 mA Voltage characteristics setting
14
Vch4
1
3.1
3.2
3.3
V
15
Vch4d
1
-30
0
30
mV
16
Supply voltage characteristics
Vch4bb
1
-80
0
80
mV
Publication data: November 2002
SDF00034AEB
5
AN32502A
Electrical Characteristics at VB1 to VB5 = 3.6 V (continued)
Note) Ta = 25C2C unless otherwise specified.
B No.
Parameter
Symbol
Test circuit
Conditions
Limits Min Typ Max
Unit
Note
MOS switch VB = 3.6 V VIN = 3.2 V, Iout = 100 mA I2C: 02H D2 bit: High VIN-V01 VB = 3.6V VIN = 3.2 V, Iout = 100 mA I2C: 02H D1 bit: High VIN-V02
17
V41 Output voltage
Vsw41
1
100
mV
18
V42 Output voltage
Vsw42
1
100
mV
General purpose output VB = 3. 6 V VDD1 = 3.2 V Iout = 1 mA VB = 3.6 V VDD1 = 3.2 V Iout = -1 mA
19
Output high level voltage
Vpoh
1
VDD -0.3
V
20
Output low level voltage
Vpol
1
0.3
V
Ch.5 LDO Output voltage LDO Output voltage VB = 3.6 V Iout = 100 mA VB = 3.6 V Iout = 100 mA/ 250 mA Output voltage difference VB = 3.4 V/ 5 V Iout = 100 mA Voltage characteristics setting
21
Vch5
1
2.716
2.8
2.884
V
22
Vch5d
1
-30
0
-30
mV
23
Supply voltage characteristics
Vch5bb
1
-30
0
30
mV
Publication data: November 2002
SDF00034AEB
6
AN32502A
Electrical Characteristics at VB1 to VB5 = 3.6 V (continued)
Note) Ta = 25C2C unless otherwise specified.
B No.
Parameter Input/ output
Symbol
Test circuit
Conditions
Limits Min Typ Max Unit Note
24
BAT_FLT detection voltage BAT_FLT return hysteresis BAT_FLT low level output voltage BAT_FLT high level output voltage Reset detection voltage Reset return hysteresis nRESET low level output voltage nRESET high level output voltage WAKEUP low level output voltage WAKEUP high level output voltage ChSW low level input voltage ChSW high level input voltage nRESETOUT low level input voltage nRESETOUT high level input voltage
Bflt
1
Lo BAT detection voltage Lo BAT detection reset voltage
Typ -2.5% Bflt 0.2 VDD1 -0.3
3.4 Bflt 0.3 VDD1 3.1 Bflt 0.3
Typ 2.5% Bflt 0.4 0.3 VDD1 0.3 Typ 2.5% Bflt 0.4 0.3
V
25 26 27 28 29 30 31 32 33 34 35 36 37
Bflth Bflt1 Bflt2 Rset Rseth Rsetv1 Rsetv2 Rwkv1 Rwkv2 Rswv1 Rswv2 Rrsv1 Rrsv2
1 1 1 1 1 1 1 1 1 1 1 1 1
V V V V

Reset detection voltage Reset detection reset voltage
Typ -2.5% Bflt 0.2
V V V V V V V V V
At no load (pulled down VDD1 only 3 M resistor internally) -0.3 VDD1 -0.3 VDD1 -0.3 VB -0.3
VDD1 VDD1 0.3 0.3
VDD1 VDD1 0.3 0.3
VDD1 VDD1 0.3 VB 0.3 VB 0.3
Publication data: November 2002
SDF00034AEB
7
AN32502A
Electrical Characteristics at VB1 to VB5 = 3.6 V (continued)
Note) Ta = 25C2C unless otherwise specified.
B No.
Parameter Serial interface
Symbol
Test circuit
Conditions
Limits Min Typ Max Unit
Note
38 39 40 41 42 43
DATA input high level DATA input low level LT input high level LT input low level LT frequency ACK drive capability
Datah Datal Cth Ctl Ctf Vack
1 1 1 1 1 1 Pull-up 4.7 k VDD = 3.2 V S2: Low Ch.2 only operation Charge circuit stopping At no load VDD = 3.2 V S2: Low Ch.2 only operation Charge circuit operation At no load VDD = 3.2 V PWR_EN: High Ch.1 only operation At no load VDD = 3.2 V S3: High Ch.3 only operation At no load VDD = 3.2 V S4: High Ch.4 only operation At no load VDD = 3.2 V Serial 01H D2: High Ch.5 only operation At no load VDD = 3.2 V All channels are operating At no load
SDF00034AEB
VDD1 -0.3 VDD1 -0.3
VDD1 0 VDD1 0
VDD1 0.3 0.3 VDD1 0.3 0.3 400 0.3
V V V V kHz V

44
Operating current 1
INC1
1
70
100
130
A
45
Operating current 2
INC2
1
80
120
150
A
46
Operating current 3
INC3
1
4
6
8
mA
47
Operating current 5
INC5
1
70
100
130
A
48
Operating current 6
INC6
1
5
8
11
mA
49
Operating current 7
INC7
1
70
100
130
A
50
Operating current 8
INC8
1
10
15
20
mA
8
Publication data: November 2002
AN32502A
Electrical Characteristics at VB1 to VB5 = 3.6 V (continued)
Note) Ta = 25C2C unless otherwise specified.
B No.
Parameter Ch.1
Symbol
Test circuit
Limits Conditions Min Typ Max Unit Note
51
DC-DC converter Transient response characteristics
Vch1ex
1
VB = 3.6 V DAC = 1000000B Iout: Change 0 mA to 200 mA Rising time 50 ns Output voltage difference V VB = 3.6 V DAC = 1000000B At no load VB = 3.6 V At no load from start up signal input till output bottom limit PWR_EN: High Oscillator frequency of the built-in oscillation circuit for ch.1
100
mV
52
DC-DC converter output ripple voltage
Vch1rr
1
40
mV
53
DC-DC converter startup time
Vch1tr
1
2
ms
54
Oscillator frequency
fdv1
1
500
kHz
Ch.2 VB = 3.6 V VBpp = 0.3 V/ 1 kHz Iout = 150 mA VB = 3.6 V VBpp = 0.3 V/ 10 kHz Iout = 150 mA VB = 3.6 V Iout: 10 mA to 200 mA Rising time 1 s Output voltage difference V VB = 3.6 V At no load from start up signal input till output bottom limit
55
LDO Ripple rejection 1 LDO Ripple rejection 2
Vch2rr1
1
-40
dB
56
Vch2rr2
1
-30
dB
57
LDO Transient response characteristics
Vch2ex
1
50
mV
58
LDO start up time
Vch2tr
1
10
ms
Note) *: The above values are reference values on design, but not guaranteed values.
Publication data: November 2002
SDF00034AEB
9
AN32502A
Electrical Characteristics at VB1 to VB5 = 3.6 V (continued)
Note) Ta = 25C2C unless otherwise specified.
B No.
Parameter Ch.3
Symbol
Test circuit
Limits Conditions Min Typ Max Unit Note
59
LDO ripple rejection 1 LDO ripple rejection 2 LDO transient response characteristics
Vch3rr1
1
VB = 3.6 V VBpp = 0.3 V/ 1 kHz Iout = 150 mA VB = 3.6 V VBpp = 0.3 V/ 10 kHz Iout = 150 mA VB = 3.6 V Iout: Change 10 mA to 200 mA Output voltage difference V VB = 3.6 V At no load from start up signal input till output bottom limit
-40
dB
60
Vch3rr2
1
-30
dB
61
Vch3ex
1
50
mV
62
LDO start up time
Vch3tr
1
10
ms
Ch.4 VB = 3.6 V Iout: Change 10 mA to 200 mA Rising time 1 s Output voltage difference V VB = 3.6 V At no load
63
DC-DC converter transient response characteristics
Vch4ex
1
100
mV
64
DC-DC converter output ripple voltage
Vch4rr
1
40
mV
65
DC-DC converter start up time
Vch4tr
1
VB = 3.6 V At no load from start up signal input till output bottom limit S4: High Oscillator frequency of the built-in oscillation circuit for ch.4
3
ms
66
Oscillator frequency
fdv4
1
500
kHz
Note) *: The above values are reference values on design , but not guaranteed values.
Publication data: November 2002
SDF00034AEB
10
AN32502A
Electrical Characteristics at VB1 to VB5 = 3.6 V (continued)
Note) Ta = 25C2C unless otherwise specified.
B No.
Parameter Ch.5 LDO ripple rejection 1
Symbol
Test circuit
Limits Conditions Min Typ Max
Unit
Note
67
Vch5rr1
1
VB = 3.6 V VBpp = 0.3 V/ 1 kHz Iout = 150 mA VB = 3.6 V VBpp = 0.3 V/ 10 kHz Iout = 150 mA VB = 3.6 V Iout = Change 10 mA / 200 mA Rising time 1 s Output voltage difference V VB = 3.6 V At no load from start up signal input till output bottom limit
-40
dB
68
LDO ripple rejection 2
Vch5rr2
1
-30
dB
69
LDO transient response characteristics
Vch5ex
1
50
mV
70
LDO start up time
Vch5tr
1
10
ms
Note) *: The above values are reference values on design , but not guaranteed values.
Publication data: November 2002
SDF00034AEB
11
AN32502A
Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin name nRESET BAT_FLT LGND CT RT SGND SCP VO1 VIN VO2 PR2 PR3 SS4 IN4 FB4 PGND4 LC4 HC4 VB5 FBR3 PGND3 LC3 VB4 PGC2 FBR2 PGND2 LC2 VB3 PGND1 LO1 HC1 VB2 O O O O O O I O O I O I O I I I I I I I I/O O O Reset output Low voltage detection output GND for input/ output part Capacitor connection pin (internal oscillator) Resistor connection pin (internal oscillator) GND (signal system) Capacitor for circuit protection VIN switch output 1 Stabilized DC voltage input VIN switch output 2 Start up control (Ch.2) Start up control (Ch.3) Soft start (Ch.4) Error amplifier inverted input (Ch.4) Error amplifier output (Ch.4) GND (Ch.4) Low side control output (Ch.4 ) High side control output (Ch.4 ) Power supply (for ch.4 output circuit) Feedback (Ch.3) GND (Ch.3) External MOS gate control (Ch.3) Power supply (Ch.3) External MOS gate control (Ch.2 reverse current protection) Feedback (Ch.2) GND (Ch.2 ) External MOS gate control (Ch.2) Power supply (Ch.2) GND (Ch.1) Low side control output (Ch.1) High side control output (Ch.1) Power supply (for ch.1 output circuit)
SDF00034AEB
Function
Publication data: November 2002
12
AN32502A
Pin Descriptions (continued)
Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin name FBR1 FB1 IN1 SS1 FBC1 FBD1 PR5 PB0 PB1 PB2 PB3 PB4 VREFDET1 VB1 FBB REGOUT BACKUP VBO VBI BO VREFDET2 PWR_EN S2 S3 S4 DATA LT VDD1 TRIG nRESETOUT PS WAKEUP I I I O O I O I I I I I I I I I/O I O I O O I I O O O O O O Feedback (Ch.1) Error amplifier output (Ch.1) Error amplifier inverted input (Ch.1) Soft start (Ch.1) External MOS gate control (Ch.5) Feedback (Ch.5) Start up control (Ch.5) General purpose output 0 General purpose output 1 General purpose output 2 General purpose output 3 General purpose output 4 Reference voltage filter Power supply (control signal system) Feedback for backup charging regulator Output for backup regulator Power supply (backup) Through output of boost DC-DC for backup Through intput of boost DC-DC for backup Control of boost DC-DC for backup Reference voltage filter (for backup circuit) Start up control input On/off control (Ch.2) On/off control (Ch.3) On/off control (Ch.4) Serial data input Serial clock input Power supply (input/ output) System switch External reset signal input I2C/ hard pin priority setting Interruption signal for CPU
SDF00034AEB
Function
O
Publication data: November 2002
13
AN32502A
Technical Data
* Circuit diagrams of the input/ output part and pin function descriptions
Note) *: The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin name TRIG (Pin 61)
Function It connect power supply voltage (VB).
VB
Inner circuit
VB 1M PAD VB
61
nRESETOUT (Pin 62)
External reset signal input: High: VB On Low : GND off (reset) CMOS input
VB 1M PAD
VB
VB
62
S1 (Pin 54)
On/off switch of ch.1: High: VDD1 On Low : GND Off CMOS input
VDD1
VDD1
VDD1
PAD
54
S2 (Pin 55)
On/off switch of ch.2: High: VB Off Low : GND On Pulled down by 1 M resistor internally. Pin 61 setting leads to determination of which to prioritize the setting of this pin or I2C serial setting.
VB
VB
VB
PAD
55
1M
S3 and S4 (Pin 56 and pin 57)
On/off switch of ch.3 to ch.4: High: VDD1 On Low : GND Off CMOS input Pulled down by 1 M resistor internally Pin 61 setting leads to determination of which to prioritize the setting of these pins or I2C serial setting.
VDD1
VDD1
VDD1
PAD
1M
PS (Pin 63)
Determining priority of I2C serial or external pin setting for ch.2, ch.3 and ch.4 on/off. High: VB I2C take priority over hard pin setting Low : GND Hard pin settings take priority over I2C CMOS input
VB
VB
VB
PAD
63
Publication data: November 2002
SDF00034AEB
14
AN32502A
Technical Data (continued)
* Circuit diagrams of the input/output part and pin function descriptions (continued)
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin Name DATA (Pin 58)
Function
Inner circuit
VDD1 VDD1 VDD1
I2C data input CMOS input
PAD
58
LT (Pin 59)
I2C clock input CMOS input
VDD1
VDD1
VDD1
PAD
59
nRESET (Pin 1)
Reset signal output Low active Pulled down by 3 M internally
VDD1
VDD1
VDD1
PAD
nRESETOUT input
1
3M
Internal RESET (VB < 3.1 V)
Publication data: November 2002
SDF00034AEB
15
AN32502A
Technical Data (continued)
* Circuit diagrams of the input/output part and pin function descriptions (continued)
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin Name
Function Output of judgment on below-threshold voltage for VB1 (Pin 45). Threshold level: 3.4 V Low active Pulled down by 1 M internally
VDD1
Inner circuit
VDD1
BAT_FLT (Pin 2)
VDD1
PAD
2
1M
WAKEUP (Pin 64)
Interrupt signal output in DVM mode High active Pulled down by 1 M internally
VDD1
VDD1
VDD1
PAD
64
1M
P0 to P4 (Pin 40 to pin 44)
General purpose output Initial setting: Low Can individual control by I2C data Output voltage is 0.3 V. (When output current is 1 mA.)
VDD1
VDD1
VDD1
PAD
Publication data: November 2002
SDF00034AEB
16
AN32502A
Technical Data (continued) 1. I2C command
1) I2C address This IC's address is `11100110'. 2) I2C sub address `_' mark shows initial setting. Sub 00H D7 D6 D5 D4 D3 D2 D1 D0
CORE_I setting DAC 7 bit 0 = Low 1 = High DVM 0 = Low 1 = High DVM change 0 = Low 1 = High Ch.2 mode 0 = Off 1 = On P2 0 = Off 1 = On 0 = Low 1 = High Ch.3 mode 0 = Off 1 = On P3 0 = Off 1 = On 0 = Low 1 = High Ch.4 mode 0 = Off 1 = On P4 0 = Off 1 = On 0 = Low 1 = High Ch.5 mode 0 = Off 1 = On V01 0 = Off 1 = On 0 0 = Low 1 = High
CORE DAC 01H
0
MODE CTL 02H
0 = Off 1=On
0 = Non Real time 1 = Real time P1 0 = Off 1 = On
0
P0 0 = Off 1 = On
V02 0 = Off 1 = On
Backup circuit 0 = Off 1 = On
GPO etc.
* Don't input another data except shown in this table. * When set D7 bit of sub address 01H, it is possible to change output voltage of ch.1 shown in sequence chart (5). In this case, setting data is latched when PWR_EN signal changes low to high. ( Non real time mode )
Publication data: November 2002
SDF00034AEB
17
AN32502A
Technical Data (continued)
2. Serial data transmission
Note) *: When a line of data is transmitted, start/ stop condition is required each time. When sub address is same, repetition of ACK and DATA allows for upgrade of settings in serial order.
Example: When all data of four lines are transmitted
Sub address
Sub address
Address
Address
ACK
ACK
ACK
ACK
ACK
Data
Data
Stop
ACK
Start
Data of the first line
Start
Data of the second line
Sub address
Stop
Sub address
Address
Address
ACK
ACK
ACK
ACK
ACK
Data
Start
Start
Data
Stop
ACK
Data of the third line
Data of the fourth line
Publication data: November 2002
SDF00034AEB
Stop 18
AN32502A
Technical Data (continued)
3. I2C serial data timing * Start condition and stop condition
DATA
tBUF
tLOW
tR
LT
tHD: STA Stop condition Start condition
tSU: STO
Stop condition
* Data recognition condition
Data line Stable state: data effective Data changeable
Data (Pin 51)
tF tHIGH LT (Pin 52)
tSU: DAT
tHD: DAT
* Recommended operating condition Parameter Time the bus must be free before a new transmission can start. Hold time start condition. After this period, the first clock pulse is generated. Low period of the clock.. Rise time of both SDA and SCL lines. Set-up time for stop condition. Set-up time data High period of the clock. Fall time of both SDA and SCL lines. Hold time data for I2C ICs. SCL clock frequency. Symbol tBUF tHD: STA tLOW tR tSU: STO tSU: DAT tHIGH tF tHD: DAT fSCL Min 1.3 0.6 1.3 0.6 100 0.6 20 0 0 Max 1000 300 0.9 400 Unit microsec microsec microsec n sec microsec n sec microsec n sec microsec kHz
Publication data: November 2002
SDF00034AEB
19
AN32502A
Technical Data (continued)
4. Backup circuit operation
in case VB < 3.1 V Ch.2 output
in case VB > 3.1 V BACKUP VB FBB
LC2
RGC2
Backup battery VBO
49
Coin battery detection SW1
48
47
Regulator for coin battery
27
24
50
VBI
51 52
Boost DC-DC control
VB
BO
Powered from coin battery
1) Coin battery detection circuit monitors pin 49 voltage. When it becomes equal to or less than 2.2 V, it make switch 1 and boost DC-DC converter off.
(To prevent over-discharge of the backup battery.)
2) Output voltage of regulator can set freely between 2.7 V and 3.3 V when set VB: 3.6 V through adjustment of
feedback voltage of pin 47.
3) Boost DC-DC converter output is set 3.2 V internally.
4) Switching to ch.2 is exercised by the intra-judging circuit.
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AN32502A
Technical Data (continued)
5. Backup circuit charging flow
START
BAT VB > 3.4 V
N DC-DC converter operate
Y MOSSW (between pin 50 and pin 51): On RGC2: Low
Coin battery < 2.2 V ? I2C setting: On ? N Y DC-DC converter stop Y N
Charging circuit operate
VB < 3.1 V ?
N
Y
RGC2: High
Stop charging circuit
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Technical Data (continued) 6-1. Sequence chart (1)
* Power on sequence
VB
S2 About 1 ms Ch.2 VDD PWR_EN
0V
3.2 V
1.3 V Ch.1
BAT_FLT nRESET
VDD
Power on reset operation depend on about 2 V. Ch.2 start up from this timing after 1 ms operation.
* Power off sequence
VB
0V Ch.1 to Ch.5
Output off BAT_FLT nRESET Low
Note) *: Power supply for input/output part is supplied from VDD, fall down same time as VDD.
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Technical Data (continued)
6-2. Sequence chart (2) * All channel operating sequence
3.525 V 3.4 V 3.1 V Operating voltage VB = 2.8 V to 5.8 V 3.4 V 3.1 V 2.0 V
3.525 V
About 2.0 V VB
(Internal reset: I2C initialize)
BAT_FLT
nRESET
S2 : Low (On) fixed
Ch.2 LDO output Coin battery charging circuit Charging circuit operating Charging circuit operating
Operate by I2C command
I2C command can be receipted after VDD1 rise up. Coin battery voltage 3.0 V 2.2V DC-DC operate DC-DC operate 2.2 V
(Backup DC-DC) Ch.2 output (VDD1) Pulled up to VDD S1 (PWE_EN)
Ch.1output
S3/ S4 (High: On)
Ch.3/ Ch.4 output
Ch.5
Operate by I2C command
Note) *: When power supply turns on, ch.2 output and charging circuit keep to off mode until battery voltage (VB) goes up to 3.525 V, even though I2C command can be receipted after power on reset operation.
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Technical Data (continued)
6-3. Sequence chart (3) * Low battery detection sequence
3.4 V 3.1 V Internal OSC 500 kHz
VBAT
CLK
BAT_FLT
VBAT < 3.4 V: Low
nRESET
VBAT < 3.1 V: Low
Ch.1
Output on
Ch.2 Output off Ch.3
Output off
Ch.4
Output off
Ch.5
Output off
Coin battery voltage
3.0 V
2.2 V
Backup boost output
Coin battery charging circuit
Output off
* BAT_FLT output changes low to high when battery voltage becomes over 3.525 V. * When RESET button is pressed, make RESET of PMIC pin output only low. Each power supply should be kept same.
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Technical Data (continued)
6-4. Sequence chart (4) * Ch.1 Sequence in case of switching ch.1 output voltage (Non real time mode) DVM bit setting for serial data allows for judgment on which switching mode to be taken, CORE_I voltage or normal on/off.
1 0
DVM bit (I2C) DAC data (I2C) PWR_EN
1010100
1000000 High
Low
Ch.1 DAC data
1000000
1010100
1.3 V
Ch.1 output voltage
1.1 V 500 sec
WAKEUP output
1) 500 sec waiting time is controlled using internal oscillator (500 kHz), and counter after PWR_EN changes high to low,
and wakeup changes low to high.
2) Internal resister hold final data.
If you want to operate in voltage switching mode and normal on/off setting, need to set DVM bit `0' by sending I2C data.
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Technical Data (continued)
6-5. Sequence chart (5) * PMIC start up
START Hard pin setting take priority over I2C initial setting Pin 62 = High ? Initial I2C setting take priority over hard pin setting N
Y VB > 3.4 V ? N
VB > 3.4 V ?
Y N
Y
Ch.2 start up
Pin 53 = High ? Y Y
Pin 54 = High ? Y
Pin 55 = High ?
Pin 56 voltage = High ? Y
Wait for control signal from CPU. *
Ch.1 start up
Ch.2 start up
Ch.3 start up
Ch.4 start up
Hard pin setting table
Note) *: Ch.2 only turns on with initial setting, when I2C start up is prioritized. Ch.5 is can be controlled only by I2C command. ( Initial setting: Off )
On Ch.1 Ch.2 Ch.3 Ch.4 High Low High High
Off Low High Low Low
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Technical Data (continued)
6-6. Sequence chart (6)
* nRESETOUT input
nRESET: Low
When VB becomes eqaul to or more than 3.4 V (Internal reset: High)
nRESET: Low output (for 50msec)
nRESET: To return high
nRESET: Each outputs keep current conditions only low output.
6-7. Sequence chart (7) * GPO operation Output setting change low to high
DATA
LT Delay time Equal to or less than 200 nsec GPO
High
Delay in output setting of change low to high is same.
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Technical Data (continued)
7-1. Voltage setting (1) VREF of each REG is set as listed below. VREF (reference value) Ch.1 1.08 V
Ch.2, Ch.3, Ch.5
1.0 V
Ch.4
1.07 V
When changing output voltage, find a resistance ratio ensuring that feedback voltages become these values.
Example: Ch.3
VB
Ch.3OUT AN32502A R1 FB
R2
Ch.3OUT = VREF x
R1 + R2 R2
Note) *: This VREF (reference value) is value in case of design.
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Technical Data (continued)
7-2. Voltage setting (2) 1) Ch.1 voltage setting from I2C Ch.1 voltage setting is possible with 7-bit DAC. Sub Address 00H 6CH Ch.1 output voltage Ch.1 VREF (reference value) 0.83 V
1.0 V
80H
1.1 V
0.92 V
A8H
1.3 V
1.08 V
Refer to sheet No.17 for I2C serial setting list. Refer to sheet No.25 for ch.1 voltage change procedure. These values are based on the premise that feedback resistance values of ch.1 are identical with the ones described on the block diagram. When this resistance ratio differs, the above-listed setting values vary.
Note) *: This VREF (reference value) is value in case of design.
* Power dissipation of package HQFN064-P-0808 1) With no radiation board soldered, there are no other patterns than the ones to be connected from each pin to the pin lands on the outer rim of PCB. 2) With radiation board soldered, another pattern of 4mm is added on the rear side of the IC. PD Ta
3.500 Mounted on standard board(grass epoxy : 50mm x 50mm x 0.8 mm) With radiation board soldering Rth(j-a) = 41.2C/W Mounted on standard board (grass epoxy : 50mm x 50mm x 0.8mm) With no radiation board soldering Rth(j-a) = 66.7C/W
3.000
Power dissipation PD (W)
2.500
2.427
2.000
1.500
1.499
1.000 0.460 Package itself Rth(j-a) = 217.1C/W 0 25 50 75 100 125 150
0.500
0.000
Ambient temperature Ta (C)
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Package schematics (Unit: mm) * HQFN064-P-0808
8.20 0.10 (8.00) 48 49 33 32 8.00 0.10 (1.10) M 4-C0.50
0.20 0.10
64 1 16
17
0.85max
0.10 0.60 0.10 (1.10) 1 64 (7.00) ( 2.00) (Depth 0.07) 16 (4.00)
Seating plane
(0.65) (0.65) 17 33 0.16 0.06 0.08
(3.35)
49
(3.35) 48 Area of no resin flash
0.40
(0 .
25
)
(4.00)
(8.00)
.1 (0 5)
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Application Notes
1. Overview This IC is a power management IC developed for Intel PXA250/ 210 and features as follows: * A single chip IC onto which to integrate ch.2 DC-DC converter, ch.3 LDO and an interface circuit for PXA250/210 * Charging circuit for backup battery, boost DC-DC converter and back-up MOS switch are built in. * Built-in ch.5 general-use output and 1 input/2 outputs analog switch are built in. * A high efficient synchronous rectifier circuit is employed for DC-DC converter. * Power supply for PXA250/ 210 core can be controlled by software (I2C interface). (Intel Reference Number: 278530-001 Core voltage changing sequence described on the document is available.) * Small-size high Pd leadless package adopted (HQFN-64) 2. Function overview * Ch.1 (Step-down DC-DC converter for CPU core) Output voltage range: 0.5 V to 1.7 V to be set up with DAC (I2C) Synchronous rectifier type Maximum current : 600 mA Operating frequency: 500 kHz * Ch.4 (Step-down DC-DC converter) Output voltage range: 1.8 V to 3.3 V Synchronous rectifier type 100% duty operation guaranteed Maximum current : 500 mA Operating frequency: 500 kHz * Ch.2, Ch.3, Ch.5 (LDO) Output voltage range: 1.8 V to 3.3 V Maximum current : 500 mA
Note) *: Maximum current conforms to a test circuit condition described on the specification.
1) DC-DC converter for backup (Boost circuit) Output voltage: 3.2 V Output current: 2 mA (typical) 10 mA (maximum) Built-in output switch MOS (Automatic on/off by main power supply) Built-in charger circuit for backup battery is built in. 2) Input/ output-related items Input I2C interface Output PWR_EN TRIG External reset input PS Analog switch input
nRESET BAT_FLT WAKEUP General purpose output (Ch.5 I2C control) Analog switch output
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Application Notes (continued)
3. System block diagram The block diagram for this IC is shown on figure 3 - 1. * Output-stage MOSFETs for ch.1 to ch.5 are fit externally for its nature general purpose. * Output current for each channel is a typical value for an evaluation board. Therefore, select an external MOSFET to meet the conditions needed in the application. * Output voltages for ch.2 to ch.5 are available in the range of 1.5 V and more with constant setting of external feedback circuit.
Ch.1 7 bit DAC Control Logic Protection circuit 3.3 V LDO Battery or AC adapter 3.0 V to 5.8 V Ch.3 3.2 V 200 mA 3.2 V LDO Li-IOn 0.85 V to 1.8 V Buck converter 0.5 V to 1.7 V 300 mA Ch.2 3.2 V 200 mA
3.2 V Buck converter
Ch.4 3.2 V Ch.5 2.8 V Backup 200 mA 500mA
2.8 V LDO
Backup battery charging circuit
3.2 V Boost General purpose Analog switch outputs
3.2 V
2 mA
Coin battery
Figure 3 - 1
4. Output voltage setting Output voltage of each channel is determined by the following equation. VREF is an internal reference voltage and differs from every each channel differs values. Refer to table 4 - 1. Ch.1 reference voltage can be controlled by DAC. 1.08 V is an initial setting value (DAC data `1010100'). A reference voltage can be set with 8.36 mV/ step in the range of 0.38 V to 1.45 V. Output voltage change is multiplied by (R1+R2)/R2. For example, when output is set to 1.3 V, the output is able to adjusted by the step of about 10 mV. Vo = VREF x (R1 + R2) R2
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Application Notes (continued)
4. Output voltage setting (continued)
* VREF
Table 4 - 1 VREF (V) Ch.1 Ch.2, Ch.3, Ch.5 Ch.4 1.08 1.0 1.07
VB
Vo AN32502A R1 R2
Figure 4 - 1 5. On/off control
* Ch.1 is controlled by the hard pin (Pin 54) only. * Ch.2, ch.3 and ch.4 are controlled by both the hard pin and I2C command.
PS pin (Pin 63) setting allows for which to prioritize. High: I2C take priority over hard pin. Low: Hard pin priority over I2C * Ch.5 is controlled by I2C only. Initial setting at time of applying supply voltage turns off. Table 5 - 1 Pin control Ch.1 Ch.2 Ch.3 Ch.4 Ch.5 I2C control
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Application Notes (continued)
6. Explanation of operation * Ch.1
VB1 VB2 PWM comparator 32 31 Q11 HO1 Q12 LO1 PGND1 FBR1 R12 R11 D11 30 VREFH 1.95 V VB1 + Error amplifier Output stage R103 4K Buffer 29 C13 OUTPUT L1
OSC CTL 7bit DAC
33
SSWC R101 R102 335k 640k
SS1
FB1
IN1
36 C12
34
35
6
SGND
Figure 6 - 1 Ch.1 is a step-down DC-DC converter. Figure 6 - 1 shows an internal block configuration. 1) Output setting Built-in a 7-bit DA converter, it allows you to set a reference voltage by the step of about 8.36 mV. In comparison between this reference voltage and FBR1 pin input voltage, a feedback control functions. Therefore, output voltage is determined by the following equation: VOUT = R11 + R12 R12 x VREF
VREF is 1.08 V of an initial setting. (DAC data `1010100') A voltage variable range is 0.38 V to 1.45 V, allowing for setting with 8.36 mV/ step (value in case of design). Refer to figure 6 - 3 for linearity of DAC. When high precision is required for output voltage, use a high precision resistor for R11 and R12, respectively. R11 and R12 are influenced not by absolute precision, but by relative precision. Therefore, when using a resistor of 0.5% precision resistor, output voltage varies for maximum 1%. 2) PWM comparison block PWM comparator controls the on period of output pulse depending on input voltage. Set output voltage to "High" and power on N-channel output MOS while triangular wave oscillation voltage is lower than pin 36 (SS1) and pin 34 (error amplifier output) voltages. Maximum duty is determined by maximum voltage of triangular oscillation and set voltage of pin 36 (SS1). This IC is set to about 88%. Insertion of a capacitor between pin 36 and GND allows for a soft start operation enabling a gradual elongation of on period of output pulse and making overshoot and undershoot smaller at the time of startup. The constant at the soft start is determined by internal R101 and an external capacitor of pin 36.
C11
R13
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Application Notes (continued)
6. Explanation of operation (continued) * Ch.1 (continued) 3) Output voltage Output voltage from HO1 and LO1 is applied with a dead time of 80 nsec so that simultaneous on of Q11 and 12 may not cause a through-current to flow. Refer to figure 2 for timing.
Off Off HO1 output Off Off
On
On
On
On
On
On
On
LO1 output Off
Off
Off
Off
80 nsec td
80 nsec td
Figure 6 - 2 4) Error amplifier Error amplifier response characteristics are determined by the feedback C11 and R13 the built-in R103 between pin 34 and pin 35. R13: 10 k C11: 0.01 F It is recommended to above In actual pattern layout, it is recommended to make C11 and R13 lines as short as possible so as to reduce effect by noise. 5) On/off control Ch.1 can be controlled only by pin 54. Control by serial data is unavailable. 6) Power supply and GND Power is supplied from pin 32 (VB2) only for the output drive stage and from pin 46 (VB1) for other parts. GND is connected for pin 29 (PGND1) only for the output drive stage. Other parts are connected to the signal system GND of pin 6 (SGND). Connect Q12 source, D11 anode, C13GND with thick wires as near to pin 29 as possible. 7) Peripheral parts The characteristics of output capacitor C13 has an effect on output transient response characteristics. It is recommended to use a high ESR capacitor like our SPCAP. It is also recommended to select the constant of 10 H for inductor L1 in the supply voltage range of this IC (2.8 V to 5.8 V) considering efficiency degradation caused by size and DC resistance.
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Application Notes (continued)
6. Explanation of operation (continued) * Ch.1 (continued) 8) DAC linearity (Ch.1)
12.0
11.5
11.0
Delta output voltage (V)
10.5
10.0
9.5
9.0
8.5
8.0 0 Measure conditions: 20d 40d 60d Bit data Output voltage: at 1.3 V setting DAC data `1010100' 80d 100d 120d 140d
Figure 6 - 3 9) Soft start timing chart
Supply voltage (VB) CT internal oscillation output 1.3 V min. SS pin voltage Output voltage 0.6 V min.
MOS gate voltage
Figure 6 - 4 Oscillation frequency of internal oscillation circuit is determined by the capacitor between pin 4 and GND and the resistor between pin 5 and GND. Oscillation frequency is 500 kHz at capacitor 33 pF and resistor 33 k (estimated constant).
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Application Notes (continued)
6. Explanation of operation (continued) * Ch.2
50 VBO VB3
28 1M R201 Gate control VREF R202
Q22 24 RGC2 Q21 27 LC2 R21 C21 C22
26 25 11
PGND2 FBR2 PR2
Figure 6 - 5 Ch.2 is a linear regulator. Figure 6 - 5 shows the ch.2 internal block configuration. It runs a feedback control comparing the internal VREF with pin 25 voltage. Output voltage is determined by the following equation. Vout = R21+R22 R22 x VREF
Internal VREF is set to 1.0 V. Ch.2 is intended to be used in the memory circuit and is automatically switched to the backup power supply circuit when supply voltage is lowered. (When VB1 gets below 3.1 V, ch.2 off, Q22 off and the backup power supply circuit on.) Q22 functions as a switch that would prevent current from reverse-flowing from output to source when switching to a backup power supply circuit. When power supply voltage (VB1) is equal to or less than 3.1 V, gate control signal becomes "High" and Q22 gate voltage becomes equal to backup for supply voltage. VBO (3.1 V to 3.3 V) and is switched off. Simultaneously, a backup power supply circuit is actuated to keep output voltage to the constant level. This switching response time is determined by Q22 gate capacitance and R201. Output voltage is likely to drop at the switching time depending on the main power supply off conditions. In this case, connect a resistor of 500 k between pins 24 and pin 50 so that R201 resistance can be kept small equivalently and response time is able to kept short. 1) Rush current at power supply input This regulator built-in a circuit limiting rush current at power supply input. Insertion of a capacitor between pin 11 (PR2) and GND allows to control rush current to approx. 500 mA. (At supply voltage: 5.8 V, C22 = 33 F) 2) On/off control This regulator is able to on/off control with a serial data and pin 55.
R22
Publication data: November 2002
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Application Notes (continued)
6. Explanation of operation (continued) * Ch.2 (continued) 3) Power supply and GND Power supply of this regulator is pin 28 (VB3) and GND is pin 26 (PGND2). VREF block is constituted by VB1 and SGND.
* Ch.3
23 VB4 Q31 VREF (1.0 V) 22
LC3 R31 C32 C31
PGND3 21 20 12 FBR3 PR3
C33
Figure 6 - 6 Ch.3 is a linear regulator circuit that is configured identically with ch.2 except for a backup switching circuit. Figure 6 - 6 shows internal block configuration of ch.3. Output voltage is determined by the following equation. Vout = R31 + R32 R32 x VREF
Internal VREF is 1.0 V. External capacitor of pin 12 is intended to control rush current on power supply. 1) On/off control This regulator is able to on/off control with serial data and pin 56. 2) Power source and GND Power supply of this regulator is pin 23 (VB4) and GND is pin 21 (PGND3). VREF block is constituted by VB1 and SGND.
R32
Publication data: November 2002
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AN32502A
Application Notes (continued)
6. Explanation of operation (continued) * Ch.4
VB1 VB5 VB5 19 HC4 OSC CTL 18 LC4 Q42 D41 17 VREF 1.07V VREFH 1.95V 16 PGND4 + SSWC R401 4K 166K R42 R41 C42 C41 R44 Q41 L4
R402
C43
R43
C44
Figure 6 - 7 Ch.4 is a step-down DC-DC converter of synchronous rectifying type. Figure 6 - 7 shows internal block configuration of ch.4. Output voltage is determined by the following equation. Vout = R41 + R42 R42 x VREF
VREF is 1.07 V initially. When high precision is required for output voltage, use a high precision resistor for R41 and R42, respectively. R41 and R42 are influenced not by absolute precision, but by relative precision. Therefore, when using a resistor of 0.5% precision resistor, output voltage varies for maximum 1%. 1) PWM comparison block PWM comparator controls the on period of output pulse depending on input voltage. Set output voltage to "High" and power on N-channel output MOS while triangular wave oscillation voltage is lower than pin 13 (SS4) and pin 14 (error amplifier output) voltages. This circuit is able to operation up to maximum duty of 100%. Insertion of a capacitor between pin 13 and GND allows for a soft start operation of gradually widening on period of output pulse at startup time so that overshoot and undershoot at startup time. The constant at the time of soft start is determined by the internal R401 and the external capacitor of pin 13. C41 and R44 are the additional components to improve transient response characteristics coming up when load current is suddenly changed. On the condition of this test board, the control output voltage on sudden load change of 0 mA to 500 mA (changing time 10 sec) Can be controlled approximately to 90 mV.
SGND
SS4
FB4
IN4
13
15
14
6
Publication data: November 2002
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Application Notes (continued)
6. Explanation of operation (continued) * Ch.4 (continued) 2) Output voltage Output voltage from HC4 and LC4 is applied with a dead time of 80 nsec so that simultaneous on of Q41 and 42 may not cause a through-current to flow. Refer to figure 6 - 8 for timing.
Off Off HC4 output
Off
Off
On
On
On
On
On
On
On
LC4 output Off
Off
Off
Off
80 nsec td
80 nsec td
Figure 6 - 8
3) On/off control Ch.4 is able to on/off control by pin 57 and serial data. 4) Power supply voltage and GND Power is supplied from pin 19 (VB5) only for the output drive stage and from pin 46 (VB1) for other parts. GND is connected from pin 16 (PGND4) only for output drive stage. Other parts are connected to the signal system GND of pin 6 (SGND). Q41 source, D41 anode and C42GND side should be connected with a fat wire as near to pin 16 as possible. 5) Peripheral parts The characteristics of output capacitor C42 has an effect on output transient response characteristics. It is recommended to use a high ESR capacitor like our SPCAP. It is also recommended to select the constant of 10 H for inductor L4 in the supply voltage range of this IC (2.8 V to 5.8 V) considering efficiency degradation caused by size and DC resistance.
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Application Notes (continued)
6. Explanation of operation (continued) * Ch.5
46 VB1
VREF ( 1.0V )
Q51 37 FBC1 C52 R52 SGND 6 38 39 FBD1 PR5 C53 C51 R51
Figure 6 - 9 Ch.5 is a linear regulator circuit that is configured identically with ch.2 except for a backup switching circuit. Figure 6 - 9 shows an internal block configuration of ch.5. Output voltage is determined by the following equation. Vout = R51 + R52 R52 x VREF
Internal VREF is 1.0 V. External capacitor C53 of pin 39 is intended to control rush current on power supply. 1) On/off control This regulator is capable of on/off control only with serial data. Initial setting turns off at IC startup. 2) Supply voltage and GND Power supply of this regulator is pin 46 (VB1) and GND is pin 6 (SGND). VREF block constituted VB1 and SGND.
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Application Notes (continued)
7. Backup charging current
VB1 46
VREF 48 CTL
REGOUT R62
R63 Backup battery
6 47
SGND
FBB
Figure 7 - 1 Figure 7 - 1 shows the configuration of a backup battery charging circuit. The circuit configuration is identical with the general linear regulator and continues to supply charging current until a backup battery voltage reaches the voltage value shown by the following equation that is a balancing condition of regulator circuit. Backup voltage = R61 + R62 R61 x VREF
Internal VREF is 1.0 V. For a lithium ion coin battery, the above voltage is set to 3.0 V. Determine R63 value according to the battery used, so as not to exceed maximum charging current specified. This circuit is automatically switched off if the main battery voltage (Pin 46, VB1) becomes equal to or less than 3.1 V. Then, a backup boost circuit starts operating. This circuit is able to setting on/off with serial data. Initial setting turns off at startup. Power supply for this circuit is supplied from pin 46 (VB1).
R61
Publication data: November 2002
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Application Notes (continued)
8. Backup boost converter
BACKUP
VREF
49
+
On
J
SET
Q
52 OSC (100 kHz) CTL
K CLRQ Off +
51
CTL MOS switch 50 to Ch.2
SGND
25 FBR2
6
Ch.2 feedback pin
Figure 8 - 1 A backup boost circuit is boost circuit of burst mode operation. Figure 8 - 1 shows internal block configuration. When the main battery voltage becomes equal to or less than 3.1 V, this circuit starts operating. Simultaneously, the internal MOS switch between pin 50 and pin 51 becomes on and this boost circuit output is supplied to the load circuit (memory circuit) on behalf of ch.2 regulator. The internal oscillation circuit starts operating when pin 50 output voltage becomes below a low side detection threshold of equal to or less than 3.1 V and it stops operation when pin 50 output voltage becomes above a high side detection threshold of equal to or more than 3.3 V. If a load current is constant, the output voltage goes down linearly. And when it reaches the above-stated low side detection voltage, the oscillating circuit operates again and starts charging an output capacitor. It stops operation when output voltage is equal to or less than 3.3 V. Then halting operation when output voltage reaches 3.3 V. An output wave form of this circuit becomes a triangular wave variable between the thresholds of 3.1 V and 3.3 V. For actual wave form, refer to figure 8 - 2 and figure 8 - 3. Low and high side detection circuits are able to detect voltage by comparing pin 25 voltage with internal reference voltage. Since pin 25 is a feedback pin for ch.2, its judging level varies according to ch.2 output voltage setting. The above-mentioned thresholds of 3.1 V and 3.3 V are based on output setting to 3.2 V. This circuit automatically becomes off when a backup battery voltage is equal to or less than 2.2 V, so as to prevent a backup battery from being over-discharged. 1) On/off control The circuit automatically operates when its main supply voltage (VB) is equal to or less than 3.1 V and its backup battery output voltage is equal to or more than 2.2 V. 2) Power supply and GND All circuit blocks are supplied from pin 49 (backup) and pin 6 is for GND.
Publication data: November 2002 SDF00034AEB
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Application Notes (continued)
8. Backup boost converter (continued)
* Backup boost converter output waveform
Change timing 3.3 V
3.2V Ch.2 output 3.1 V
Pin 24 voltage
nRESET output
Pin 52 voltage
Figure 8 - 2
Switching at 100 kHz in the burst area.
Pin 52 output voltage waveform
Pin 52 output current waveform
Figure 8 - 3
Publication data: November 2002 SDF00034AEB
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Application Notes (continued)
9. General purpose (GPO0 to GP05)
60 Change VB1 to VDD1 Internal logic Level shift Pin 40 to pin 44 PO to P4 VDD1
3
LGND
Figure 9 - 1 This IC is equipped with 5-system general purpose output pins. Figure 9 - 1 shows circuit configuration. The output is CMOS mode. Initial setting at startup is low for every outputs and high/ low settings are carried out by I2C control. DC characteristics of output MOSFET become output voltage 0.3 V at 1 mA. It is able to applied for on/off switch of external circuits or for driving LED. But care should be taken to voltage loss by the above-mentioned DC resistance of output MOSFET for actual application. 1) Power supply and GND Power supply voltage of this regulator is pin 60 (VDD1) and GND is for pin 3 (LGND). Internal logic block preceding level shift is VB1 and SGND.
10. Analog switch (VO1, VO2)
I2C
Control logic
9
8
10
DC voltage regulator input
DC output 1
DC output 2
Figure 10 - 1 This IC built-in an analog switch of 1 input 2 outputs. This is pin 9 for input and pin 8 and pin 10 for outputs. Figure 1 shows circuit configuration. The MOS size between pin 8 and pin 9 is same as the one between pin 9 and pin 10. P-channel MOSFET is connected between pin 8 and pin 9 and between pin 9 and pin 10. It is used as switch by logic control of gate. Suppose you have to supply the same stabilized supply voltage to both A and B circuit blocks. You can use this analog switch to halt B block to save the power while A block is operating. Initial setting at power on turns off for both and on/off setting is able to done by I2C control. DC resistance of switching MOS is about 1 . Care should be taken to this influence for current and load fluctuation.
Publication data: November 2002
SDF00034AEB
45

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